1. Technical Field
Various exemplary embodiments of the inventive concept relate to a semiconductor device and a method for fabricating the same, and more particularly, to a semiconductor device having a vertical channel transistor and a method for fabricating the same.
2. Related Art
With increase in the integration degree of semiconductor devices, a channel length of transistors is increasingly reduced. Short channel effects such as Drain Induced Barrier Lowering (DIBL), a hot carrier effect, and a punch through are caused due to the reduction in the channel length.
As various methods of preventing such effects from being caused, methods of increasing a channel length by reducing a length of a junction region or by forming a recess in a channel region of a transistor are suggested.
However, as the integration degree of the semiconductor devices is approaching Giga bits, it is difficult to satisfy the restricted device area in a flat transistor structure in which junction regions are formed at both sides of a gate electrode even when the channel length thereof is scaled down. Therefore, a vertical channel transistor is suggested.
A semiconductor device having a vertical channel transistor in the related art will be described with reference to FIG. 1.
The semiconductor device in the related art includes a plurality of pillars 215 vertically extending, that is, protruding from a semiconductor substrate 210, a gate insulating layer 230 surrounding a lateral surface of each pillar 215, and a gate electrode 240 surrounding each pillar 215 surrounded with the gate insulating layer 230 with a predetermined height. A silicide layer 260 is formed on a top surface of the pillar 215, and an electrode 270 is formed on the silicide layer 260.
With scaling down in the semiconductor device having the vertical channel transistor, specifically, a phase-change random access memory (PCRAM), the level of difficulty in a process is seriously increased. In particular, in the semiconductor device of 20 nm grade or less, ON current is reduced by increase in a contact resistance due to the scaling down.
Therefore, there is a need for a method for increasing ON current by reducing a contact resistance.